The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to an apparatus and method of making strained channel complementary metal oxide semiconductor (CMOS) transistors.
Both theoretical and empirical studies have demonstrated that carrier mobility in a transistor can be greatly increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. Stress is defined as force per unit area. Strain is a dimensionless quantity defined as the unit change, for example a percentage change, in a particular dimension of an item, in relation to the initial dimension of that item. An example of strain is the change in length versus the original length, when a force is applied in the direction of that dimension of the item: for example in the direction of its length. Strain can be either tensile or compressive. In p-type field effect transistors, the application of a compressive longitudinal stress, i.e. in the direction of the length of the conduction channel, creates a strain in the conduction channel which is known to increase the drive current of a PFET. However, if the same compressive stress is applied to the conduction channel of an NFET, its drive current decreases. However, when a tensile stress is applied to the conduction channel of an n-type field effect transistor (NFET), the drive current of the NFET increases.
Accordingly, it has been proposed to increase the performance of an NFET by applying a tensile longitudinal stress to the conduction channel of the NFET, while increasing the performance of a PFET by applying a compressive longitudinal stress to its conduction channel. Several ways have been proposed to impart different kinds of stresses to different regions of a wafer that house NFET and PFET transistors. In one example, mechanical stress is manipulated by altering the materials in shallow trench isolation regions (STIs) disposed adjacent to the conduction channels of FETs to apply a desired stress thereto. Other proposals have centered on modulating intrinsic stresses present in spacer features. Yet other proposals have focused on introducing etch-stop layers such as those that include silicon nitride.